Cores of System-on-Chip are usually powered by power converters located outside the System-on-Chip on a separate integrated circuit. FIG. 1 shows a System-on-Chip 11, wherein the chip boundary is indicated by a dotted line. The System-on-Chip 11 comprises a plurality of cores 12 (core-1, . . . , core-n) wherein each core is powered by a separate power converter 13 of a plurality of power converters. Alternatively, each core may share a power converter with a number of different cores. It can be observed that each power converter 13 comprises a switchable power stage 16, a driver 15 and a controller 14, each located outside the System-on-Chip. Each power converter 13 is a switched DC-DC converter. Each power converter comprises a plurality of phases per power stage 16 and controller 14. Each controller 14 implements a control law for determining a control signal for controlling the driver 15 which drives the power stage 16 by a digital pulse width modulation (DPWM) signal. The driver comprises a pulse width modulator generating the DPWM signal for switching the switchable power stage. The control signal generated for controlling the driver is a duty ratio defining a duty cycle of the DPWM signal. The duty ratio and repetition rate might be regulated on cycle to cycle bases. Furthermore, the System-on-Chip comprises a plurality of power rails (rail-1, rail-2, rail-x), each comprising a power rail chip interface 110. A power rail connects a power converter 13 with a core 12. Furthermore, means for dynamic voltage and frequency scaling are provided on the System-on-Chip 18 that are connected to each controller 14 of a power converter 13 via a slow peripheral control-bus 19 from control bus chip interface 111 onwards. The controller processes the information provided by the means for dynamic voltage and frequency scaling for determining the control signal. The slow peripheral control-bus 19 is located outside the System-on-Chip.